Committee Chair

Craven, Stephen D.

Committee Member

Eltom, Ahmed; Yaqub, Raziq

Department

Dept. of Electrical Engineering

College

College of Engineering and Computer Science

Publisher

University of Tennessee at Chattanooga

Place of Publication

Chattanooga (Tenn.)

Abstract

The use of partial reconfiguration (PR) in reconfigurable systems such as Field Programming Gate Arrays (FPGAs) has gained a lot of attention during the past ten years. Recently, Xilinx has released the first commercially available PR implementation for its FPGAs. However, there is a lack of educational tools for PR instruction. In addition, the design and implantation of PR on FPGAs can be beneficial compared with the current communications tools within academia. This thesis presents the design and simulation of several basic modulation schemes within Simulink and System Generator for educational applications in communications classes. In addition, the implementation process of creating and testing additional partial bitstreams will take a few minutes rather than a few hours, which make this reconfigurable system a suitable system for educational applications. Furthermore, each modulation scheme can be implemented without any use of Hardware Description Language (HDL), embedded, and software development design. After implementing these models on an FPGA the results of these implementations are analyzed and compared with the simulation results. The results demonstrate the proper implementation of these PR designs on FPGAs.

Degree

M. S.; A thesis submitted to the faculty of the University of Tennessee at Chattanooga in partial fulfillment of the requirements of the degree of Master of Science.

Date

5-2011

Subject

Adaptive computing systems

Keyword

Field programming gate arrays; Partial reconfiguration

Discipline

Electrical and Computer Engineering | Engineering

Document Type

Masters theses

Extent

xii, 53 leaves

Language

English

Rights

Under copyright.

License

http://creativecommons.org/licenses/by-nc-nd/3.0/

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